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1 ut54acs162245s radhard schmitt cmos 16-bit bidirectional multipurpose low voltage transceiver datasheet march 12, 2003 features voltage translation - 3.3v bus to 2.5v bus - 2.5v bus to 3.3v bus cold sparing all pins 0. 25 m c ommercial radhard tm cmos - total dose: 3 00krad ( si) and 1mrad(si) - single event latchup immune high speed, low power consumption schmitt trigger inputs to filter noisy signals cold and warm spare - all outputs available qml q or v processes standard microcircuit drawing 5962-02543 package: - 48-lead flatpack, 25 mil pitch (.390 x .640) description the 16-bit wide ut54acs162245s multipurpose low voltage t ransceiver is built using aeroflex utmc?s commercial radhard tm epitaxial cmos technology and is ideal for space applications. this high speed, low power ut54acs162245s low voltage transceiver is designed to perform multiple func- tions including: asynchronous two-way communication, schmitt input buffering, voltage translation , warm and cold sparing. with v dd equal to zero volts, the ut54acs162245s outputs and inputs present a minimum impedance of 1m w mak- ing it ideal for "cold spare" applications. balanced outputs and low "on" output impedance make the ut54acs162245s well suited for driving high capacitance loads and low impedance backplanes. the ut54acs162245s enables system designers to interface 2.5 v olt cmos compatible components with 3.3 volt c mos components. for voltage translation, the a port in- terfaces with the 2.5 v olt bus; the b port interfaces with the 3.3 volt b us. the direction control (dirx) controls the direction of data flow. the output enable ( oe x) overrides the direction con- trol and disables both ports. these signals can be driven from either port a or b. the direction and output enable controls operate these devices as either two independent 8-bit transceiv- ers or one 16-bit transceiver. logic symbol pin description pin names description oe x output enable input (active low) dirx direction control inputs xax side a inputs or 3-state outputs (2.5 v port) xbx side b inputs or 3-state outputs (3.3v port) (48) oe 1 g2 (47) 1a1 (46) 1a2 (44) (2) 1b1 (5) (3) 1b2 1a3 (43) 1a4 (41) 1a5 (40) 1a6 1b3 (9) 1b6 (8) 1b5 (6) 1b4 (38) 1a7 (37) 1a8 (12) 1b8 (11) 1b7 (1) dir1 1en1 (ba) 1en2 (ab) 11 12 (25) oe 2 g1 (24) dir2 21 22 (36) 2a1 2b1 (13) (35) 2a2 (33) 2a3 (32) 2a4 (30) 2a5 (29) 2a6 (27) 2a7 (26) 2a8 (16) 2b2 2b3 (20) 2b6 (19) 2b5 (17) 2b4 (23) 2b8 (22) 2b7 (14) 2en1 (ba) 2en2 (ab)
2 pinouts power table when v dd2 is at 2.5 v olts, either 2.5 o r 3.3 volts c mos logic levels can be applied to all control inputs. for proper operation connect power to all v dd and ground all v ss pins (i.e., no float- ing v dd or v ss input pins). tie unused inputs to v ss . a lways insure v dd1 > v dd2 during operation of the part. function table cold/warm spare function the device will place all outputs into a high-impedance state if either v dd supply is taken to zero volts (i ws , warm spare), or if both v dd supplies are set to zero volts (i cs , cold spare). device power up function the device will place all outputs into a high-impedance during power-up. the high impedance state is maintained for a time period approximately equal to the rise time of v dd1 . 1 2 3 4 5 7 6 48 47 46 45 44 42 43 dir1 1b1 1b2 v ss 1b3 1b4 vdd1 oe 1 1a1 1a2 v ss 1a3 vdd2 8 41 1b5 1a5 1a4 9 40 1b6 1a6 10 39 v ss v ss 48-lead flatpack top view 1b7 1b8 2b1 2b2 v ss 2b3 2b4 vdd1 2b5 2b6 11 12 13 14 15 17 16 18 19 20 v ss 2b7 2b8 dir2 21 22 23 24 38 37 36 35 34 32 33 1a7 1a8 2a1 2a2 v ss 2a4 31 vdd2 2a3 30 2a5 29 2a6 28 v ss 27 2a7 26 2a8 25 oe 2 port b port a operation 3.3 volts 2.5 v olts voltage translator 3.3 volts 3.3 volts non translating 2.5 v olts 2.5 volts non translating enable oe x direction dirx operation l l b data to a bus l h a data to b bus h x isolation
3 logic diagram 1a1 1a2 1a3 1a4 1a5 1a6 1a7 1a8 dir1 (1) (47) (48) (2) (46) (3) (44) (5) (43) (6) (41) (8) (40) (9) (38) (11) (37) (12) 1b1 1b2 1b3 1b6 1b5 1b4 1b8 1b7 oe 1 2a1 2a2 2a3 2a4 2a5 2a6 2a7 2a8 dir2 (24) (36) (25) (13) (35) (14) (33) (16) (32) (17) (30) (19) (29) (20) (27) (22) (26) (23) 2b1 2b2 2b3 2b6 2b5 2b4 2b8 2b7 oe 2 2 . 5 v p o r t 3 . 3 v p o r t 2 . 5 v p o r t 3 . 3 v p o r t
4 radiation hardness specifications 1 notes: 1. logic will not latchup during radiation exposure within the limits defined in the table. 2. not tested, inherent to cmos technology. absolute maximum ratings 1 note: 1. stresses outside the listed absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. exposure to absolute maxim um rating conditions for extended periods may affect device reliability and performance . 2. for cold spare mode (v dd1 =vss, v dd2 =vss), v i/o may be -0.3v to the maximum recommended operating level of v dd1 +0.3v. 3. maximum junction temperature may be increased to +175 o c during burn-in and life test. dual supply operating conditions parameter limit units total dose 1.0e5 rad ( si) sel latchup >1 13 mev-cm 2 /mg neutron fluence (note 2) 1.0e14 n/cm 2 symbol parameter limit (mil only) units v i/o (note 2) voltage any pin -.3 to v dd1 +.3 v v dd1 supply voltage -0.3 to 4 .0 v v dd2 supply voltage -0.3 to 4 .0 v t stg storage temperature range -65 to +150 c t j (note 3) maximum junction temperature +1 50 c q jc thermal resistance junction to case 20 c/w i i dc input current 10 ma p d maximum power dissipation 1 w symbol parameter limit units v dd1 supply voltage 2.3 t o 3 .6 v v dd2 supply voltage 2.3 t o 3.6 v v in input voltage any pin 0 to v dd1 v t c temperature range -55 to + 125 c
5 dc electrical characteristics 1 ( -55 c < t c < +125 c) symbol parameter condition min max unit v t + schmitt trigger, positive going threshold 2 v dd from 2.3 to 3.6 .7v dd v v t - schmitt trigger, negative going threshold 2 v dd from 2.3 to 3.6 .3v dd v v h1 schmitt trigger range of hysteresis 9 v dd from 3.0 to 3.6 0.5 v v h2 schmitt trigger range of hysteresis 9 v dd from 2.3 to 2.7 0.4 v i i n input l eakage current 9 v dd from 2.7 to 3.6 v in = v dd or v ss -1 3 m a i oz three-state o utput leakage current 9 v dd from 2.7 to 3.6 v in = v dd or v ss -1 3 m a i cs cold sparing input leakage current 3,11 v in = 3.6 v dd = v ss -5 5 m a i ws warm sparing input leakage current 3,11 v in = v ss or v dd, v dd1 = 0, v dd2 = v dd or v dd1 = v dd, v dd2 = 0 -5 5 m a i os1 short-circuit output current 5, 10 v o = v dd or v ss v dd from 3.0 to 3.6 -200 200 ma i os2 short-circuit output current 5, 10 v o = v dd or v ss v dd from 2.3 to 2.7 -100 100 ma v ol1 low-level output voltage 9 i ol = 8ma i ol = 100 m a v dd = 3.0 0.4 0.2 v v ol2 low-level output voltage 9 i ol = 8ma i ol = 100 m a v dd = 2.3 0.4 0.2 v v oh1 high-level output voltage 9 i oh = -8ma i oh = -100 m a v dd = 3.0 v dd - 0.7 v dd - 0.2 v v oh2 high-level output voltage 9 i oh = -8ma i oh = -100 m a v dd = 2.3 v dd - 0.7 v dd - 0.2 v
6 dc electrical characteristics 1 ( -55 c < t c < +125 c) notes: 1. all specifications valid for radiation dose 1e5 rad ( si) per mil-std-883, method 1019. 2. functional tests are conducted in accordance with mil-std-883 with the following input test conditions: v ih = v ih (min) + 20%, - 0%; v il = v il (max) + 0%, - 50%, as specified herein, for ttl, cmos, or schmitt compatible inputs. devices may be tested using any input voltage within the above specified range, but are guaranteed to v ih (min) and v il (max). 3. all combinations of oe x and dirx 4. guaranteed by characterization. 5. not more than one output may be shorted at a time for maximum duration of one second. 6. power does not include power contribution of any cmos output sink current. 7. power dissipation specified per switching output. 8. capacitance measured for initial qualification and when design changes may affect the value. capacitance is measured between the designated terminal and v ss at frequency of 1mhz and a signal amplitude of 50mv rms maximum. 9.guaranteed; tested on a sample of pins per device. 10. supplied as a design limit, but not guaranteed or tested. 11. zero volts is defined as 0.0 volts +/- 0.25volts. 12. v dd1 and v dd2 voltage rise is monotonic. 13. rise time measured from v dd @ zero volts to v dd @ greater than 2.3 v. symbol parameter condition min max unit p total1 power dissipation 4,6,7 c l = 40pf 6.2 mw/ mhz v dd from 3.0v to 3.6v p total2 power dissipation 4,6,7 c l = 40pf 3 mhz v dd from 2.3v to 2.7v i dd standby supply current v dd1 or v dd2 v in = v dd or v ss v dd = 3.6v oe = v dd pre-rad 25 o c 10 m a oe = v dd pre-rad -55 o c to +125 o c 475 m a oe = v dd post-rad 25 o c 15 ma c in input capacitance 8 f = 1mhz @ 0v 15 pf v dd from 2.3v to 3.6v c out output capacitance 8 f = 1mhz @ 0v 15 pf v dd from 2.3v to 3.6v por v dd1 & v dd2 power-on 4,13 v dd1 or v dd2 zero volt offset 250 mv v dd1 and v dd2 rise-time 12 500 ms
7 ac electrical characteristics 1 (port b = 3.3 v olt, port a = 2.5 v olt) (v dd1 = 3.0v to 3.6v; v dd2 = 2.3v to 2.7v , -55 c < t c < +125 c) notes: 1. all specifications valid for radiation dose 1e5 rad(si) per mil-std-883, method 1019. 2. dirx to bus times are guaranteed by design, but not tested. oe x to bus times are tested 3. output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-h igh symbol parameter minimum maximum unit t plh propagation delay data to bus 2 10 ns t phl propagation delay data to bus 2 10 ns t pzl output enable time oe x to bus 2 12 ns t pzh output enable time oe x to bus 2 12 ns t plz output disable time oe x to bus high impedance 2 15 ns t phz output disable time oe x to bus high impedance 2 1 5 ns t pzl 2 output enable time dirx to bus 2 12 ns t pzh 2 output enable time dirx to bus 2 12 ns t plz 2 output disable time dirx to bus high impedance 2 15 ns t phz 2 output disable time dirx to bus high impedance 2 15 ns t slh 3 t shl 3 skew between outputs (40pf +/- 10 pf on each output) skew between outputs (40pf +/- 10 pf on each output) 0 0 900 900 ps ps t plz t pzh t pzl t phl t phz propagation delay i nput output v dd v dd /2 0v t plh v oh v ol v dd /2 control input 3.3v o utput normally low enable disable times 3.3v output normally high v dd v dd /2 0v v dd /2 v dd /2 .8 v dd .2 v dd v dd /2+0.2 v dd /2-0.2 .2 v dd + .2v .8 v dd - .2v t plz t pzh t pzl t phz 2.5v o utput normally low 2.5v output normally high v dd /2 v dd /2 .7 v dd .2 v dd v dd /2+0.2 v dd /2-0.2 .2 v dd + .2v .7 v dd - .2v
8 ac electrical characteristics 1 (port a = port b, 3.3 volt operation) (v dd1 = 3.0 to 3.6v; v dd2 = 3. 0v to 3 .6v, -55 c < t c < +125 c) notes: 1. all specifications valid for radiation dose 1e5 rad(si) per mil-std-883, method 1019. 2. dirx to bus times are guaranteed by design, but not tested. oe x to bus times are tested 3. output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-h igh symbol parameter minimum maximum unit t plh propagation delay data to bus 2 7.5 ns t phl propagation delay data to bus 2 7.5 ns t pzl output enable time oe x to bus 2 10 ns t pzh output enable time oe x to bus 2 10 ns t plz output disable time oe x to bus high impedance 2 12 ns t phz output disable time oe x to bus high impedance 2 12 ns t pzl 2 output enable time dirx to bus 2 10 ns t pzh 2 output enable time dirx to bus 2 10 ns t plz 2 output disable time dirx to bus high impedance 2 12 ns t phz 2 output disable time dirx to bus high impedance 2 12 ns t slh 3 t shl 3 skew between outputs (40pf +/- 10 pf on each output) skew between outputs (40pf +/- 10 pf on each output) 0 0 900 900 ps ps t plz t pzh t pzl t phz control input 3.3v o utput normally low enable disable times 3.3v output normally high v dd v dd /2 0v v dd /2 v dd /2 .8 v dd .2 v dd v dd /2+0.2 v dd /2-0.2 .2 v dd + .2v .8 v dd - .2v t phl propagation delay i nput output v dd v dd /2 0v t plh v oh v ol v dd /2
9 ac electrical characteristics 1 (port a = port b, 2.5 v olt operation) (v dd1 = 2.3v to 2.7v; v dd2 = 2.3v to 2.7v , -55 c < t c < +125 c) notes: 1. all specifications valid for radiation dose 1e5 rad(si) per mil-std-883, method 1019. 2. dirx to bus times are guaranteed by design, but not tested. oe x to bus times are tested 3. output skew is defined as a comparison of any two output transitions high-to-low vs. high-to-low and low-to-high vs. low-to-h igh symbol parameter minimum maximum unit t plh propagation delay data to bus 2 10 ns t phl propagation delay data to bus 2 10 ns t pzl output enable time oe x to bus 2 12 ns t pzh output enable time oe x to bus 2 12 ns t plz output disable time oe x to bus high impedance 2 15 ns t phz output disable time oe x to bus high impedance 2 15 ns t pzl 2 output enable time dirx to bus 2 12 ns t pzh 2 output enable time dirx to bus 2 12 ns t plz 2 output disable time dirx to bus high impedance 2 15 ns t phz 2 output disable time dirx to bus high impedance 2 15 ns t slh 3 t shl 3 skew between outputs (40pf +/- 10 pf on each output) skew between outputs (40pf +/- 10 pf on each output) 0 0 900 900 ps ps t plz t pzh t pzl t phl t phz propagation delay i nput output v dd v dd /2 0v t plh v oh v ol v dd /2 control input 2.5v o utput normally low enable disable times 2.5v output normally high v dd v dd /2 0v v dd /2 v dd /2 .7v dd .2 v dd v dd /2+0.2 v dd /2-0.2 .2 v dd + .2v .7v dd - .2v
10 package figure 1. 48-lead flatpack 1. all exposed metalized areas are gold plated over electroplated nickel per mil-prf-38535. 2. the lid is electrically connected to vss. 3. lead finishes are in accordance with mil-prf-38535. 4. lead position and colanarity are not measured. 5. id mark symbol is vendor option. 6. with solder, increase maximum by 0.003. 6 4 5 6
11 ordering information ut54acs162245s: smd lead finish: (c) = gold (a) = solder case outline: (x) = 48 lead fp class designator: (q) = class q (v) = class v device type (01) = 16-bit multipurpose low voltage t ransceiver d rawing number: 02543 total dose: (r) = 1e5 rad ( si) (f) = 3e5 rad(si) (g) = 5e5 rad(si) (h) = 1e6 rad(si) federal stock class designator 5962 r 02543 01 * * * notes: 1. total dose radiation must be specified when ordering. qml q and qml v not available without radiation hardening.
12 ut54acs162245s ut54 *** ****** * * * lead finish: (c) = gold (a) = solder screening: (c) = mil temp (p) = prototype package type: (u) = 48-lead fp part number: (16225slv) = 16-bit multipurpose low voltage transceiver i/o type: (acs) = cmos compatible i/o level utmc core part number notes: 1. military temperature range flow per utmc manufacturing flows document. devices are tested -55c, room temp, and 125c. radiation n either tested nor guaranteed. 2. prototype flow per utmc manufacturing flows document tested at 25c only. lead finish is gold only.

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